This invention relates to integrated circuits and, more particularly, to interconnect circuitry in integrated circuits.
Integrated circuits may include many components such as inputs, outputs, memory blocks, logic circuits, etc. Interconnect circuitry in the integrated circuit may route signals over wires among these components.
In an effort to ease chip design and to provide a simple and regular layout, many integrated circuits may include multiple instantiations of a same tile of interconnect circuitry, which may be repeated across the entire integrated circuit. Each tile of interconnect circuitry may include two or more parallel tracks. Each track is a lane that may route at most one wire in parallel.
A tile of interconnect circuitry often has at least one wire starting in a given track and at least one other wire ending in another track with all other wires changing tracks. The change in tracks (e.g., every wire may be shifted one track to the right) is sometimes also referred to as wire twisting.
A wire that spans L tiles overlaps a neighboring wire for L-1 tiles in such a configuration. As design geometries shrink, a reduction in the spacing between wires may result in increased interconnect capacitance, which may be further exacerbated by the long spatial overlap between the adjacent wires. Situations frequently arise where signal delays are affected by effects such as crosstalk in which a signal toggling in an aggressor wire slows down the signal transition in a victim wire.